The HCS12 9S12: An Introduction to Software and Hardware by Han-Way Huang

By Han-Way Huang

This new booklet presents a complete answer for studying and educating embedded procedure layout in keeping with the Freescale HCS12/9S12 microcontroller. Readers will research step by step tips to application the HCS12 utilizing either meeting and C languages, in addition to tips to use such improvement instruments as CodeWarrior, ImageCraft ICC12, MiniIDE, GNU C, and EGNU IDE. Supportive examples sincerely illustrate all purposes of the HCS12 peripheral features, together with parallel port, timer features, PWM, UART port, SPI, I2C, CAN, on-chip flash and EEPROM programming, exterior reminiscence enlargement, and extra. New sections on C programming sort, software program improvement technique, and software program reuse were further in theis revision. A back-of-book CD comprises the resource code for all examples within the booklet, a number of teams of reusable software features, and complimentary freeware improvement instruments for greater studying.

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The variations of the indexed addressing mode are described in the following subsections. 7 Indexed Addressing Modes with Constant Offsets The syntax of the indexed addressing mode with constant offset is as follows: n, r where n is a 5-bit, 9-bit, or 16-bit constant r is the base register and can be X, Y, SP, or PC For example, ldaa 4,X ; A ← [4 1 [X]] loads the contents of the memory location with the address equal to the sum and 4 and X into A. 9 ■ 27 HCS12 Addressing Modes For example, staa ; m[[B] 1 [X]] ← [A] B, X stores the contents of A in the memory location of which the address equals the sum of the contents of B and X.

R = base register (may be X, Y, or SP). 10 16-Bit Offset Indexed Indirect Mode The syntax of this addressing mode is as follows: [n, r] where n is the 16-bit offset r is the base register and can be X, Y, SP, or PC In this mode, the HCS12 fetches the actual effective address from the memory location with address equal to the sum of the 16-bit offset and the contents of the base register and then uses that effective address to access the operand. The square brackets distinguish this addressing mode from 16-bit constant offset indexing; for example, ldaa [10, X] In this example, index register X holds the base address of a table of pointers.

At the end of this read cycle, the PC is incremented to 0x000A. The opcode byte 0xE0 is fetched. Step 3 The control unit recognizes that the current instruction requires performing a read operation to the data memory with the address specified by the ptr register. The processor places the 16-bit value of the ptr register on the data memory address bus and indicates this is a read operation. 6 ■ 19 Program Execution Step 4 The data memory returns the contents to the processor and the processor places it in accumulator A.

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